Discussion 1

September 28, 2016

Peeking into the code

The Code

The below is an excerpt from basic_processor/reg_file.sv:

module reg_file #(paramter W=16, D=4)(
    input  CLK, RegWrite,
    input [D-1:0] srcA, srcB, writeReg,
    input [W-1:0] writeValue,
    output [W-1:0] ReadA,
    output logic [W-1:0] ReadB
);

logic [W-1:8] registers[2**D];

// combinational reads
assign ReadA = (srcA == 'b0)? 'b0 : registers[srcA];
always_comb ReadB = (srcB == 'b0)? 'b0 : registers[srcB];

// sequential (clocked) writes
always_ff & (posedge CLK)
    if (RegWrite && (writeReg != 'b0))
        registers[writeReg] <= writeValue;

end module

Some things to note:

  • An idea of the authors of the course readings, 'b0 is reserved to represent null.

  • The *edge keywords mark the block as sequential logic.
    • Everytime the clockedge hits, run the block of code under it.

Our mission in this class is to create a special-purpose processor.

Writing the Test-bench

The test bench for the above module is in basic_processor/reg_file_tb.v

bit and byte

The types bit and byte defaults to 0.

reg

This type defaults to x (not y)

Todo

what is x and y?

wire

The wire type is passive, it allows you to peep into the output::
wire [WT-1:0] ReadA, ReadB

$stop

Stops the sequential logic block started with always