Introduction

CSE 141L - Lecture 1 - Week 1 - September 26, 2016


Housekeeping

Discussion

  • Monday and Wednesday 3:00pm and 4:00pm
  • Open attendance policy

Lecture

  • All sections are podcaster

Grading

  • 4 Labs, each about ~25% of total grade

FPGA

  • Field programmable Gate Array
  • Macro Architecture
    • Array of logic cells, memory
  • Micro Architecture
    • Anatomy of a logic cell

Anatomy of a cell

  • Understanding how flow control works on the hardware level
  • Adaptive LUT (Look-up Table)
  • Design Flow (Logic Synthesis)

Verilog

SystemVerilog

  • The language we use in this class